Integrated circuits have become extremely large and complex, typically including millions of components. Accordingly, the design of integrated circuits is also very complex and time consuming, involving synthesizing, analyzing and optimizing many circuit parameters. Because of this complexity, electronic design automation (EDA) systems have been developed to assist designers in developing integrated circuits at multiple levels of abstraction.
In EDA systems, static timing analysis (STA) modules are used to analyze and optimize the timing parameters of an integrated circuit design. These modules typically analyze the timing of a circuit design using nominal or worst case timing values. However, due to semiconductor process and environmental variations, the actual circuit delays rarely assume their respective nominal or worst case timing values. Thus, statistical static timing analysis (SSTA) tools have been developed to perform timing analysis on circuit designs using probabilities for the circuit delay values.